Recently, transistors with an underlapped gate structure have been widely studied to overcome several challenges associated with nanoscale devices. In this work, underlap region is incorporated at source and drain (S/D) ends in a fully depleted Strained Silicon On Insulator (SSOI) device, with high-k dielectric material in the spacer region. The S/D underlapped region helps to reduce the leakage current and can be particularly useful for low power applications.However, increased underlap length degrades the ON current significantly. We show that this issue can be mitigated via the inclusion of a high-k spacer, which improves the ON current by enhancing the gate controllability over the S/D underlap channel region. It helps to achieve the essential requirement low power applications i.e. the high ON/OFF current ratio at extremely low value of leakage current. The strained silicon material is used in the channel region to further improve the ON current. A compact threshold voltage model is developed for the proposed device (underlap-SSOI) while maintaining the accuracy at par with TCAD simulations. This threshold voltage model incorporates underlap length, strain-induced offsets and spacer dielectric constant. This device model may be used for circuit simulations.