Conventional array multiplier based on carry save adders is optimized in this letter. Some specific full adders in the adders array for partial products accumulation are simplified without any cost. By modifying the logic expressions of two special full adders, circuit complexity is reduced, resulting in decreased power dissipation and propagation delay. Static circuit structures for the adders are provided to demonstrate the effectiveness. Furthermore, logical AND gates to produce partial products are redesigned to save area and power. The layout regularity of array multiplier is well preserved. Circuit simulation shows that speed and power can be improved 9.7% and 3.1% for a 4*4 structure, and the number of transistors decreases 5.3%.

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