For pursuing a more comprehensive mechanism of void formation at the Sn/Cu interface, different grain size Cu samples with and without twinned boundaries are electrodeposited for the Sn/Cu joint and the IMC analysis. The formation of voids in the Sn/Cu joint is divided into three parts for discussion: Cu diffusion, Sn diffusion, and impurity diffusion. For the void formation at the Cu/Cu3Sn interface, the concept of the mechanism is from the Kirkendall effect, which is specially focused on the speed difference of Cu diffusion between at the Cu grain boundary and in the copper lattice in this study. The speed difference caused the vacancy formation. Impurities also play an important role in promoting the vacancy aggregation from a cluster to a void. Whether it is a diffusion effect or an impurity effect, it occurs at a Cu grain boundary. The voids would be formed when the density of the Cu grain boundary is high. The grain size of Cu is inversely proportional to the density of the Cu grain boundary; as a result, Cu grain size strongly affects the interfacial microstructure of a Sn/Cu joint, that is, the larger the Cu grain size is, the less the void at the Sn/Cu interface will be formed.

This study focuses on the effects of plating additives and forced convection on microstructure and surface roughness of a copper foil at high current densities. A pilot Cu plating bath was designed according to the simulation of flow field using COMSOL Multiphysics. Accordingly, accurate fluid flow rates and the streamline patterns thereof were obtained in this work. The surface roughness of copper deposit depended on the limiting current density of cupric ions, the distribution of adsorbed chloride ions and the adsorbed organic additives at high current densities (10∼60 A·dm−2). Forced convection has strong influence on these factors as mentioned above. A copper foil with low surface roughness could be consequently obtained for the application of high frequency transmission in printed circuit board industry.

In recent years, the butterfly technique (BFT1) was developed to achieve through-hole (TH) filling of a printed circuit board (PCB) by copper electroplating.1It not only can operate in direct current plating but also perform a void-free TH filling. However, a thick copper layer is plated on the surface of a PCB to cause a dimple issue on the TH opening. The dimple on the TH opening has to be leveled off, otherwise the following build-up process cannot be performed because there are a lot of dimples on the inner copper layer. In this work, we adjusted the plating formula to overcome the dimple issue of BFT for TH filling. The plating result shows that a thin copper layer plated on the PCB surface is obtained and the dimple is significantly improved. The enhancement in the TH copper filling performance is beneficial to the build-up process of advanced PCB. Keywords: Through-hole filling, Printed circuit board, Dimple, Copper Electroplating     Reference W. P. Dow, H. H. Chen, M. Y. Yen, W. H. Chen, K. H. Hsu, P. Y. Chuang, H. Ishizuka, N. Sakagawa, R. Kimizuka, “Through-Hole Filling by Copper Electroplating”, Journal of The Electrochemical Society, 2008, 155, D750-D757. Figure 1

Recently, a copper electroplating technique, namely butterfly technique (BFT) [1], was developed to achieve a void-free filling of a through hole (TH) of a printed circuit board (PCB). However, the BFT for TH filling caused an issue of thick copper layer on the PCB surface, which increases the process cost due to a requirement of post copper etching process. Literature has mentioned that copolymers have strong suppression on copper electroplating than poly(ethylene glycol) (PEG). The strong suppressor can minimize surface copper thickness to achieve excellent filling performance. In this work, we employ a copper filling formula to perform the TH filling. Several copolymers were employed as suppressors to replace PEG. The result shows that the surface copper thickness is decreased by using the copolymer. It can not only enhance the copper filling performance but also increase plating efficiency. Reference W. P. Dow, H. H. Chen, M. Y. Yen, W. H. Chen, K. H. Hsu, P. Y. Chuang, H. Ishizuka, N. Sakagawa, R. Kimizuka, “Through-Hole Filling by Copper Electroplating”, Journal of The Electrochemical Society, 2008, 155, D750-D757. Figure 1