The characterization of spatially heterogeneous hydraulic conductivity (K) is important in groundwater resources management. We propose a Bayesian statistical method that integrates multiple secondary data (continuous and category data) with primary data (K) to improve regional K field characterization. Considering the disparity of the data scale, spatial scarcity of primary and secondary data, and need for regional-scale site characterization, the aquifer thickness is used as the scale for data integration. We transform the high-resolution secondary data to the scale of K and perform linear/ nonlinear regression analyses for the transformed secondary data and primary data. A Bayesian approach using Metropolis-within-Gibbs sampling is developed for jointly integrating the primary and transformed secondary data without a limitation on the type of data attribute and the number of data set. A synthetic example is first presented to demonstrate the capability of the proposed method. Results show that the correlation strength, not the relation type, is the primary factor for improving the estimates. The Bayesian method is applied to Choushui River alluvial fan in Taiwan. Resistivity logs and a lithological description are first upscaled and then simultaneously integrated in the K estimation. Results indicate that the improvement of the K estimate obtained using resistivity data is higher in the proximal and mid fans but lower in the distal fan compared to that obtained using lithofacies data. Jointly integrating two-attribute data outperforms using one or no secondary data set for K estimates. The proposed Bayesian integration method is thus versatile and suitable for large-scale aquifer characterization.

With the emerging SoC era the on-chip embedded memory will occupy most of the silicon real estate. As the technology proceeds into very deep submicron, the yield of SoCs will drop sharply mainly because of the on-chip memory failure. Therefore, the embedded memory is becoming the crucial part for achieving higher chip yield. In this paper, we propose an errorresilient video data memory system architecture design. The proposed scheme employs partial memory protection scheme rather than traditional whole memory protection. Our approach is based on the fact that video data memory need not to be error-free because multimedia data has built-in redundancies by their own nature and allows partial data loss without serious quality degradation. With our approach we can achieve 100% data memory yield while incurring a small power overhead. We demonstrate the efficiency of our approach with H.264 application up to 2.0% memory bit error.