Object detection has made great progress in recent years, the two-stage approach achieves high accuracy and the one-stage approach achieves high efficiency. In order to inherit the advantages of both while improving detection performance, this manuscript present a useful method, named Densely Connected Refinement Network (DCRN). It adds the dense connection based on RefineDet. Compare to the RefineDet, our approach can take full advantage of the bottom feature information. DCRN is formed by three interconnected modules, the dense anchor refinement module (DARM), the dense object detection module (DODM) and the dense transfer connection block (DTCB). First module can make better use of the features from different layers to initially adjust anchors by attaching dense connection. The latter module takes the refined anchors to further improve the regression and predict multi-class label. Due to the dense connection in DCRN, the network parameters are reduced and the computing costs of this approach is also saved. Extensive experimental results on PASCAL VOC 2007 and PASCAL VOC 2012 demonstrate that DCRN achieves higher accuracy than the one-stage method and higher efficiency than the two-stage method.

Convolutional neural networks (CNN) have become essential for many scientific and industrial applications, such as image classification and pattern detection. Among the devices that can implement neural networks, SRAM based FPGAs are a popular option due to their excellent parallel computing capability and good flexibility. However, SRAM-FPGAs are susceptible to radiation effects, which limits its application on safety critical applications. In this paper, the reliability of an accelerator based on the advanced Instruction-Set Architecture is evaluated based on hardware fault injection experiments. Each main module of the accelerator is evaluated separately, and the impact of parallelism and model features on the accelerator reliability is also examined. The experimental results reveal some important conclusions in terms of general hardware reliability and also of the particular model reliability. First, over 99% of SEUs on the computation modules will cause accuracy loss, and the reliability improves for higher parallelism. Second, a large portion of SEUs on the data mover and the instruction scheduler will cause system corruptions due to abnormal interactions with the ARM or other modules. Third, nonlinear activation and pooling layers are effective in reducing the effect of SEUs on computation modules, so models that use these layers tend to be more robust. The results provide a deep understanding of the impact of errors on CNNs implemented on ISA based FPGA accelerators (e.g., the Xilinx DPU).