No abstract

No abstract

We have developed a low-temperature formation technique for ferroelectrics (<500 °C), which is crucial for the ferroelectric random access memory (FeRAM) to be embedded in a leading-edge complementary metal oxide semiconductor (CMOS). A 53-nm-thick Bi4Ti3O12 film was successfully formed by metalorganic chemical vapor deposition at 450 °C and subsequent annealing at 500 °C. It was found that perovskite grains preferentially orient along the (110) and (111) directions and that the fabricated Bi4Ti3O12 capacitors show a remnant polarization (2Pr) of as large as 25.7 µC/cm2. In addition, we have adopted a nondestructive readout operation (NDRO) technique to extend read cycle endurance, in which the switched polarization at reading is automatically rewritten by readout voltage removal. We have demonstrated stable readout characteristics at more than 1011 cycles for 0.18 µm NDRO FeRAMs.

No abstract

We present an analysis of carrier dynamics of the single-photon detection process, i.e., from Geiger mode pulse generation to its quenching, in a single-photon avalanche diode (SPAD). The device is modeled by a parallel circuit of a SPAD and a capacitance representing both space charge accumulation inside the SPAD and parasitic components. The carrier dynamics inside the SPAD is described by time-dependent bipolar-coupled continuity equations (BCE). Numerical solutions of BCE show that the entire process completes within a few hundreds of picoseconds. More importantly, we find that the total amount of charges stored on the series capacitance gives rise to a voltage swing of the internal bias of SPAD twice of the excess bias voltage with respect to the breakdown voltage. This, in turn, gives a design methodology to control precisely generated charges and enables one to use SPADs as conventional photodiodes (PDs) in a four transistor pixel of a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) with short exposure time and without carrier overflow. Such operation is demonstrated by experiments with a 6 µm size 400 × 400 pixels SPAD-based CIS designed with this methodology.