With the majority of users migrating to a cloud computing platform, the responsibility for data security has increased considerably. As data with various levels of sensitivity moves out of the confines of the system firewall, there is no control over where it resides; it depends on the cloud server being used. This makes the use of secured cryptographic algorithms necessary to improve data security and maintain the confidentiality of data. The encryption algorithm used most extensively today is the Advanced Encryption Standard (AES). Hardware acceleration with Field Programmable Gate Array can improve the performance of AES. This study examines various approaches for improving data encryption methods that can be utilized as hardware accelerators to improve the fundamental AES cipher. Some research publications suggest ways to boost throughput while others advise ways to save area and power. Many subsequent developments have also used other cryptographic methods such as RSA and ECC to improve key management security. This study examines the outcomes of multiple ways for metrics including throughput, area, power, and data security, and explains some of the best implementation solutions for each metric individually.

Now‐a‐days advanced cryptographic algorithms are needed in order to improve data security and confidentiality. One such algorithm used prominently is advanced encryption standard (AES) algorithm. AES is a complex algorithm with multiple rounds of processing data and occupies more space or area when implemented on hardware. Since each sub‐step of computation has a similar structure, the proposed method employs the novel idea of using the same hardware to implement the AES functionality. Hence the number of logical units occupied are leveraged. The proposed scheme, Mux‐Demux pair method (MDP), uses a mux‐demux structure. It is implemented on Virtex‐7 and ZynQ7000 FPGAs and the code is written in Verilog HDL language in the Vivado software. The proposed work when simulated on Virtex‐7 occupies an area of 1932 slices, giving an optimized throughput of 10.167 Gbps while the work simulated on ZynQ7000 occupies an area of 3253 slices, resulting in a throughput of 23.858 Gbps.