The network of genes which mediates multiple drug resistance in yeast includes, among others, the PDR1 gene, which encodes a putative regulator of gene expression, and PDR5, a locus whose amplification leads to resistance. We demonstrate that disruption of PDR5 causes marked hypersensitivity not only to cycloheximide but also to sulphometuron methyl and the mitochondrial inhibitors chloramphenicol, lincomycin, erythromycin and antimycin. Genetic analysis of double mutants containing an insertion in PDR5 (pdr5:Tn5), which renders cells hypersensitive to cycloheximide, and a pdr1 mutation, which confers resistance to this inhibitor, indicates that the expression of resistance requires a functional PDR5 gene. The same interdependency is observed for chloramphenicol, but not for oligomycin, lincomycin, erythromycin or sulphometuron methyl. Northern analysis of PDR1 and PDR5 transcripts reveals that the 5.2 kbp PDR5 transcript is overexpressed in pdr1 (resistant) mutants, but underexpressed in a disruption of PDR1. These observations provide strong experimental support for our former proposal that the PDR5 gene is a target for regulation by the PDR1 gene product.

The next generation Opteron ™ processor integrates 4 enhancedperformance x86 cores, each with 512kB L2 cache and an enhanced 128-bit FPU. The cores are integrated with a shared 2MB L3 cache and an enhanced on-chip memory controller that supports up to 4 16-bit HyperTransport ™ links and a dual-channel 128-bit DDR2/DDR3 interface. The design contains nearly 450M transistors and is fabricated in a 65nm SOI CMOS process with dual stress liners and embedded SiGe for PMOS source/drains. The design uses 11 layers of copper interconnect (Fig. 5.4.1) that include advanced low-k dielectrics. In a 95W max power envelope, the target frequency is 2.2 to 2.8GHz at 1.15V. The SoC chip is designed to facilitate maximum reuse of functional components and to provide the flexibility to create targeted variations.The processor is based on a flexible clocking architecture designed to easily scale across die configurations. Each core contains its own PLL, clock distribution system, and power grid, which can be independently power/performance managed by varying the frequency and voltage. The core voltage and the individual core frequencies are independent of the on-chip Northbridge, allowing them to enter power-efficient states while the processor interface runs at full speed to service DDR memory and HyperTransport ™ traffic. The clock distribution system is designed for a worst case systematic skew of 12ps in each core.To provide clocking flexibility and reduce communication latency between the processor and the northbridge, an asynchronous FIFO buffer absorbs the global clock skews and clock rate variations. The FIFO enables a modular design style when building die with a large number of cores and is fundamental to minimizing the core-to-Northbridge latency. A synchronous mode is provided in the FIFO buffer for tester determinism. To provide reverse compatibility with previous AMD Opteron ™ processors, this chip incorporates only one differential clock receiver to receive the 200MHz clock reference. The reference clock is distributed across the die to each core PLL, Northbridge PLL, HyperTransport ™ link, and DDR memory interface. The reference clock network contains special power-supply-filtered buffers to reduce the clock jitter created by a large clock-tree network. For thermal control, each of the 4 cores contains 8 remote temperature sensors scattered across the core and connected to a thermal evaluation (TCEN) circuit. The Northbridge contains 6 additional remote sensors connected to a fifth TCEN circuit. The 5 TCEN circuits are connected to a global thermal control (TCON) circuit that instructs the remote controllers to collect thermal measurements and report the results. The remote sensor contains a diode array and additional control circuits. The temperature is determined by measuring voltage drops while forcing a range of currents. The TCEN block contains differential switched-capacitor integrators that perform the arithmetic operations and convert the analog temperature into a 9-bit digital value. A first-order ∆Σ conve...

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Gallium Arsenide Metal Semiconductor Field Effect Transistors (GaAs MESFETs) are used in analog Microwave Monolithic Integrated Circuits (MMICs) because of their high frequency response.Common applications for MMICs include low noise and power amplifiers for use in satellite communication and missile guidance systems. The performance of MESFETs is improved with smaller gate lengths, but to consistently achieve the highest performance, control methods must be in place for the critical processes. Gate length control is the key parameter in maintaining the RF performance and a lack of gate pinch off is the major yield loss category. This paper will describe the process and the tools that Texas Instruments uses to monitor the critical parameters. It will also describe the control methods and review the major contributors to variations in the process. . INTRODUCTIONThe use of 0.25 m gate lengths is becoming common for production of the highest performing circuits. To avoid performance degradation associated with higher line resistance, the gates are formed with a "T' shaped cross-section. The top of the gate, or cap, is larger (0.7-1.0 jim) than the trunk, the portion making contact with the surface. Figure 1 shows an SEM micrograph of a cross-sectioned gate. The trunk is the most critical dimension of the gate; its length determines the input capacitance of the FET and therefore controls the speed of the device. Figure 1. SEM micrograph of T-gate cross-section. PROCESSThe gates are defined using electron beam lithography using an Hitachi HL 700 M/D Ebeam. Figure 2 shows the process flow schematic. Three layers of resist are used to create an opening for the gate. From bottom to top the layers are 4% PMMA, EBR-9 (1) and 2% PMMA. The structure is exposed with two passes. The first pass exposes the trunk and uses a relatively high dose. The second Ebeam pass exposes the cap utilizing a smaller dose than for the trunk. The structure is developed in MIBK. The developer dissolves the EBR9 much flister than PMMA leaving a 0.25 .tm opening in the bottom layer of PMMA and a larger opening fij. the cap. The top layer overhangs the EBR9 forming a lip that assists in lifting the evaporated metal that is used to form the actual gate. 0-8194-149 1-3/94/$6.00 278/SPIE Vol. 2196 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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