We present a 5 MSample/s current steering digitalto-analog converter which has a programmable resolution between 8 bit, 10 bit and 12 bit. A selectable 2-D unary matrix architecture and a resolution programmable decoder are proposed for the resolution programmability. The proposed current steering digital-to-analog converter is implemented in a 22 nm FD-SOI (Fully Depleted Silicon-on-Insulator) CMOS technology. The simulation verifications of the CS-DAC at three resolution modes are made. The maximum DNL of 0.06 LSB is obtained at 8 bit resolution modes, and the maximum INL (Integral Non-Linearity) of 0.53 LSB is obtained at 12 bit resolution modes. The minimum SFDR (Spurious-Free Dynamic Range) of 47.93 dBc is obtained at 8 bit resolution mode.