It is of great significance to improve the driving range prediction accuracy to provide battery electric vehicle users with reliable information. A model built by the conventional multiple linear regression method is feasible to predict the driving range, but the residual errors between -3.6975 km and 3.3865 km are relatively unfaithful for real-world driving. The study is innovative in its application of machine learning method, the gradient boosting decision tree algorithm, on the driving range prediction which includes a very large number of factors that cannot be considered by conventional regression methods. The result of the machine learning method shows that the maximum prediction error is 1.58 km, the minimum prediction error is -1.41 km, and the average prediction error is about 0.7 km. The predictive accuracy of the gradient boosting decision tree is compared against that of the conventional approaches.

193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its patterning capability to about 20nm using the double-patterning technique [1]. Despite the non-trivial sub-20nm patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology. 25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements.In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including 300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.

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With the major advances made in internet of vehicles (IoV) technology in recent years, usage-based insurance (UBI) products have emerged to meet market needs. Such products, however, critically depend on driving risk identification and driver classification. Here, ordinary least square and binary logistic regressions are used to calculate a driving risk score on short-term IoV data without accidents and claims. Specifically, the regression results reveal a positive relationship between driving speed, braking times, revolutions per minute and the position of the accelerator pedal. Different classes of risk drivers can thus be identified. This study stresses both the importance and feasibility of using sensor data for driving risk analysis and discusses the implications for traffic safety and motor insurance.