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In this paper, we propose a conversion method from pipelined synchronous Register Transfer Level (RTL) models into pipelined asynchronous RTL models with bundled-data implementation. To know data-path resources controlled by each pipeline stage, the proposed method generates a control data flow graph (CDFG) from synchronous RTL models. After generating the CDFG, the proposed method generates asynchronous RTL models by analyzing each pipeline stage on the CDFG, assigning asynchronous control modules, and connecting the control modules to the data-path resources. In addition, we also propose optimization methods during the conversion. In the experiment, we converted four pipelined synchronous RTL models into pipelined asynchronous ones. In addition, we performed logic synthesis for the converted asynchronous RTL models to check the quality of the asynchronous RTL models. The synthesized asynchronous circuits without the optimization methods could reduce the energy consumption by 1.47% on average compared to synchronous circuits. Moreover, the optimization methods could reduce the energy consumption by 15.12% on average compared to synchronous circuits.

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