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Concern on stresses in solder bumps/underfill and warpage of flip chip BGA packages increases recently because reliability of flip chip packages relates directly to the corresponding stresses and warpage. In addition, when die size increases, the problem becomes more annoying. This problem is mainly due to mismatch in the coefficient of thermal expansion (CTE) and Young's modulus for materials made of substrate, silicon chip, underfill, and solder joints. In this paper, CTE for BT substrates were measured using electronic speckle pattern interferometry (ESPI) in different manufacturing stages to understand the effect of via drilling, Cu plating and patterning, and solder mask coating. The effect due to solder mask coating on CTE change was found to the most significant. Further, the CTE of BT substrates used in wire bond BGA packages and flip chip BGA packages varied significantly due to use of different core materials and different thickness of solder mask. On warpage measurement, 40x40 mm FCBGA with die size equal to 10x10, 20x20, and 26x26mm and thickness equal to 730 and 400um were employed and the measurement was performed from room temperature up to 225 o C. The phase-shifted shadow moiré technique was adopted for this warpage measurement. 2D and 3D finite element models were also constructed to analyze the warpage and stresses of these FC BGA packages. It was found that with accurate CTE data of the substrate as the input the predicted warpage was in excellent agreement with the experimental data, which made it possible to perform meaningful parametric analyses and optimal design of large-sized FC BGA packages.

Die cracking is an annoying problem in the packaging industry.In our previous study, we have identified the weak region of the chip strength distribution in a wafer using the threepoint bending test. It was found that the strength of the chips within the weak region was 30% to 50% lower than the averaged chip strength of the whole wafer, and the cause of the weak region was due to backside mechanical grinding. In this paper, additional thousands of chips on different wafers were tested to find the solution to enhance the chip strength in these weak regions, which included the effects of grinding speed, fine grinding depth, post processing using plasma etching or polishing, and search of optimal polishing depth.It was found from the experimental results that (a) slow down the grinding speed can increase chip strength in both the weak region and the whole wafer by approximately 50%, (h) although use of polishing after mechanical grinding increased the chip strength in the weak region, only 1 to 2 umthick polishing is considered adequate. On the other hand, use of coarse mechanical giinding only reduced the chip strength drasticany to about 20% of the original value.

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