This paper presents a power-and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm 2 ASIC, implemented in a low-voltage 0.18 m CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages, and employ a mismatch-scrambling technique to prevent the ripple signal associated with mismatch between these stages from limiting the dynamic range. In addition, an ultra-low-power LNA architecture is proposed to increase the power-efficiency of the receive circuitry. The ASIC has a compact, element-matched layout, and consumes less than 230 mW while receiving. Its functionality has been successfully demonstrated in 3-D imaging experiments.

This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

Abstract:We report a plasmon steering method that enables us to dynamically control the direction of surface plasmons generated by a two-mode slit in a thin metal film. By varying the phase between different coherent beams that are incident on the slit, individual waveguide modes are excited. Different linear combinations of the two modes lead to different diffracted fields at the exit of the slit. As a result, the direction in which surface plasmons are launched can be controlled. Experiments confirm that it is possible to distribute an approximately constant surface plasmon intensity in any desired proportion over the two launching directions. We also find that the anti-symmetric mode generates surface plasmons more efficiently than the fundamental symmetric mode.

This paper presents a power-and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm 2 ASIC, implemented in a low-voltage 0.18 m CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages, and employ a mismatch-scrambling technique to prevent the ripple signal associated with mismatch between these stages from limiting the dynamic range. In addition, an ultra-low-power LNA architecture is proposed to increase the power-efficiency of the receive circuitry. The ASIC has a compact, element-matched layout, and consumes less than 230 mW while receiving. Its functionality has been successfully demonstrated in 3-D imaging experiments.