Arithmetic Logic Units are one of the vital unit in general purpose processors and major source of power dissipation. In this paper we have demonstrated an optimized Arithmetic and Logic Unit through the use of an optimized carry select adder. Carry select adders have been considered as the best in their category in terms of power and delay. In this context a full adder optimized in terms of power has been used in synthesizing a carry select adder. Combined with the new adder structure, there is a substantial improvement in terms of power and delay. The total device power and hierarchy power has been reduced to 12.5 % and 53.39 % respectively. 3 % reduction in total completion time has also been observed. The circuit has been synthesized on kintex FPGA through Xilinx 14.3 using 28 nm technology in Verilog HDL and results has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment.

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