Two-dimensional (2D) semiconductors have attracted considerable attention in recent years. However, to date, there is still no effective approach to produce large-scale monolayers while retaining their intrinsic properties. Here, we report a simple mechanical exfoliation method to produce large-scale and high-quality 2D semiconductors, by designing an atomically flat Au-mesh film as the peeling tape. Using our prefabricated mesh tape, the limited contact region (between the 2D crystal and Au) could provide enough adhesion to mechanically exfoliate uniform 2D monolayers, and the noncontact region (between the mesh holes and monolayers) ensures weak interaction to mechanically release the 2D monolayers on desired substrates. Together, we demonstrate a scalable method to dry exfoliate various 2D monolayer arrays onto different substrates without involving any solutions or contaminations, representing the optimization between material yield, scalability, and quality. Furthermore, detailed optical and electrical characterizations are conducted to confirm their intrinsic quality. With the ability to mechanically exfoliate various 2D arrays and further restacking them, we have demonstrated large-scale van der Waals heterostructure arrays through layer-to-layer assembling. Our study offers a simple and scalable method for dry exfoliating 2D monolayer and heterostructure arrays with intrinsic material quality, which could be crucial to accelerate fundamental investigations as well as practical applications of proof-of-concepts devices.

Van der Waals (vdW) metallic contacts have been demonstrated as a promising approach to reduce the contact resistance and minimize the Fermi level pinning at the interface of two-dimensional (2D) semiconductors. However, only a limited number of metals can be mechanically peeled and laminated to fabricate vdW contacts, and the required manual transfer process is not scalable. Here, we report a wafer-scale and universal vdW metal integration strategy readily applicable to a wide range of metals and semiconductors. By utilizing a thermally decomposable polymer as the buffer layer, different metals were directly deposited without damaging the underlying 2D semiconductor channels. The polymer buffer could be dry-removed through thermal annealing. With this technique, various metals could be vdW integrated as the contact of 2D transistors, including Ag, Al, Ti, Cr, Ni, Cu, Co, Au, Pd. Finally, we demonstrate that this vdW integration strategy can be extended to bulk semiconductors with reduced Fermi level pinning effect.

The detection of ultraviolet (UV) radiation with effective performance and robust stability is essential to practical applications. Metal halide singlecrystal perovskites (ABX 3 ) are promising next-generation materials for UV detection. The device performance of all-inorganic CsPbCl 3 photodetectors (PDs) is still limited by inner imperfection of crystals grown in solution. Here wafer-scale single-crystal CsPbCl 3 thin films are successfully grown by vapor-phase epitaxy method, and the as-constructed PDs under UV light illumination exhibit an ultralow dark current of 7.18 pA, ultrahigh ON/OFF ratio of ≈5.22 × 10 5 , competitive responsivity of 32.8 A W −1 , external quantum efficiency of 10867% and specific detectivity of 4.22 × 10 12 Jones. More importantly, they feature superb long-term stability toward moisture and oxygen within twenty-one months, good temperature tolerances at low and high temperatures. The ability of the photodetector arrays for excellent UV light imaging is further demonstrated.

A single device with switchable functions is highly attractive to the growing demands of complex optoelectronics. However, most of the currently reported devices either exhibit a lack of multifunction operation or require complex electrode configurations with limited performances. Here, a new concept of a functionalized‐black phosphorus (f‐BP)/MoS2 heterojunction is proposed, which enables the coexistence of an optoelectronic memory and a detector in a single device. The oxidation‐induced artificial‐traps on the BP surface result in a gate‐modulated photogating effect, so that the device can be freely switched between memory and detector by simply changing the back‐gate voltage. In the memory model, the device has an ultra‐long storage time (10 years), an ultra‐high on/off ratio (3.5 × 107), and outstanding multi‐bit storage (≈90 states), while in the detector model, the device still exhibits a fast response (130/260 µs), an impressive responsivity (22.2 A W−1), and self‐driven broadband detection (ultraviolet to near‐infrared). Most importantly, the highly anisotropic BP enables fast NIR polarization resolution with a maximum polarization ratio of 6.98 at 1064 nm.

Vertical field effect transistors (VFETs) have attracted considerable interest for developing ultra‐scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, representing another dimension for high‐density transistors. However, high‐density VFETs with small pitch size are difficult to fabricate and is largely limited by the trade‐offs between drain thickness and its conductivity. Here, a simple approach is reported to scale the drain to sub‐10 nm. By combining 7 nm thick Au with monolayer graphene, the hybrid drain demonstrates metallic behavior with low sheet resistance of ≈100 Ω sq−1. By van der Waals laminating the hybrid drain on top of 3 nm thick channel and scaling gate stack, the total VFET pitch size down to 20 nm and demonstrates a higher on‐state current of 730 A cm−2. Furthermore, three individual VFETs together are vertically stacked within a vertical distance of 59 nm, representing the record low pitch size for vertical transistors. The method pushes the scaling limit and pitch size limit of VFET, opening up a new pathway for high‐density vertical transistors and integrated circuits.