<p>This study reviews related studies on the impact of the layout dependent effects on high frequency and RF noise parameter performances, carried out over the past decade. It specifically focuses on the doughnut and multi- finger layouts. The doughnut style involves the polygonal and the 4- sided techniques, while the multi-finger involving the narrow-oxide diffusion (OD) and multi-OD. The polygonal versus 4-sided doughnut, and the narrow-OD with multi-fingers versus multi-OD with multi- fingers are reviewed in this study. The high frequency parameters, which are of concern in this study, are the cut- off frequency (f_T) and the maximum frequency (f_MAX), whereas the noise parameters involved are noise resistance (R_N) and the minimum noise figure (NF_min). In addition, MOSFET parameters, which are affected by the layout style that in turn may contribute to the changes in these high frequency, and noise parameters are also detailed. Such parameters include transconductance (G_m); gate resistance (R_g); effective mobility (μ_eff); and parasitic capacitances (c_gg and c_gd). Investigation by others has revealed that the polygonal doughnut may have a larger total area in comparison with the 4- sided doughnut. It is also found by means of this review that the multi-finger layout style with narrow-OD and high number of fingers may have the best performance in f_T and f_MAX, owing partly to the improvement in G_m, μ_eff, c_gg, c_gd and low frequency noise (LFN). A multi-OD with a lower number of fingers may lead to a lower performance in f_T due to a lower G_m. Upon comparing the doughnut and the multi-finger layout styles, the doughnuts appeared to perform better than a standard multi-finger layout for f_T, f_MAX, G_m and μ_eff but are poorer in terms of LFN. It can then be concluded that the narrow-OD multi-finger may cause the increase of c_gg as the transistor becomes narrower, whereas a multi-OD multi-finger may have high R_g and therefore may lead to the increase of f_T and f_MAX as the transistor becomes narrower. Besides, the doughnut layout style has a higher G_m and f_T, leading to larger μ_eff from the elimination of shallow trench isolation (STI) stress.</p>

In typical stimulated Raman scattering (SRS) signal extraction, the photodetector and lock-in amplifier are often based on separate platforms, rendering the system cumbersome and non-scalable. This paper proposes an SRS double-demodulation lock-in amplifier implemented with a complementary metal-oxide semiconductor (CMOS) image sensor technology that integrates two-stage 1/f noise and offset reduction circuits with a high-speed lateral electric field modulation (LEFM) photo-demodulator. A weak SRS signal is buried in a large offset with a ratio of 10−4 to 10−6; boosting such signals in a CMOS device requires an extremely high offset and noise reduction capability. The double-modulation two-stage lock-in amplifier demodulates at 40 MHz with a sampling frequency of 20 MHz, can suppress the laser and circuit’s 1/f noise to achieve higher detection sensitivity. A prototype chip fabricated using 0.11 μm CMOS image sensor technology is evaluated. Both simulation and measurement results are presented to verify the functionality and show that the differential readout structure can successfully reject laser common mode components while emphasizing its differences. The measurement results show that the double-modulation lock-in amplifier effectively suppresses the circuit’s 1/f noise by a factor of nearly two decades.

Accurate transistor thermal noise model is crucial in IC design as it allows accurate selection of transistors for specific frequency application. The accuracy of the model is represented by the similarity between the simulated and the measured noise parameters (NPs). This work was based on a problem faced by a foundry concerning the dissimilarities between the measured and simulated NPs, especially minimum noise figure (NF_min) for frequencies below 3 GHz.

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