Logic Circuits Are 2D semiconductors ready for next‐generation IC application? In article number 2202472, Yufeng Xie, Lifeng Bian, Wenzhong Bao, and co‐workers present a wafer‐scale demonstration by circuit‐level fabrication on a 4‐inch MoS2 wafer. While pass‐transistor configuration is more like an expedient to build logic circuits based on n‐type MoS2, future development should add complementary p‐type 2D semiconductors to realize more complex ICs.

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This paper presents a high-gain D-band power amplifier (PA) fabricated with 28-nm CMOS technology for a sub-terahertz frequency modulated continuous wave imaging system. It adopts two-channel power combining using artificial transmission lines to absorb the parasitic capacitance of the ground-signalground pad. The layout of the transistors and neutralization capacitors are optimized to improve the maximum stable gain, stability, and robustness. Asymmetrically magnetically coupled resonators are used in inter-stage and input matching networks to extend the operating bandwidth. The PA achieves a peak power gain of 21.9 dB and maximum output power of 11.8 dBm with 10.7% of power-added efficiency. Also, this PA can achieve higher than 10 dBm output power over the frequency range of 120-150 GHz.INDEX TERMS D-band, power amplifier (PA), sub-terahertz (sub-THz), CMOS, power combining, imaging system, frequency modulated continuous wave (FMCW).

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This paper presents a single-pole 32-throw (SP32T) switch with an operating frequency of up to 6 GHz for 5G communication applications. Compared to the traditional SP32T module implemented by the waveguide package with large volume and power, the proposed switch can significantly simplify the system with a smaller size and light weight. The proposed SP32T scheme utilizing tree structure can dramatically reduce the dc power and enhance isolation between different output ports, which makes it suitable for low-power 5G communication. A design methodology of a novel transmission (ABCD) matrix is proposed to optimize the switch, which can achieve low insertion loss and high isolation simultaneously. The average insertion loss and the isolations are 1.5 and 35 dB at 6 GHz operating frequency, respectively. The switch exhibits the measured input return loss which is better than 10 dB at 6 GHz. The 1 dB input compression point of SP32T is 15 dBm. The prototype is designed in 5 V 0.25 μm GaAs technology and occupies a small area of 12 mm2.