No abstract

A parameter extraction procedure for staggered-type organic field-effect transistors (OFETs), in which only the electrical characteristics of a single device are needed, was newly considered. The existing differential method and the transition voltage method for evaluating contact and channel parameters in OFETs were complementarily combined. The calibration of the total resistance between the source and the drain was also incorporated to compensate discrepancies in the total resistances calculated from output and transfer characteristics, caused by the existence of nonignorable contact resistance and carrier traps. By using our proposed method, gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact pentacene thin-film transistors, and the channel-length dependence of these parameters was investigated. A series of results of parameter extraction confirm the validity of our proposed method, which is advantageous in avoiding the influences of characteristic variations that are frequently observed in practical OFET devices.

Contact effects in organic thin-film transistors (OTFTs) were examined by using our previously proposed parameter extraction method from the electrical characteristics of a single staggered-type device. Gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact (BGTC) pentacene TFTs with active layers of different thicknesses, and for pentacene TFTs with contact-doped layers prepared by coevaporation of pentacene and tetrafluorotetracyanoquinodimethane (F4TCNQ). The extracted parameters suggested that the influence of the contact resistance becomes more prominent with the larger active-layer thickness, and that contact-doping experiments give rise to a drastic decrease in the contact resistance and a concurrent considerable improvement in the channel mobility. Additionally, the estimated energy distributions of trap density in the transistor channel probably reflect the trap filling with charge carriers injected into the channel regions. The analysis results in this study confirm the effectiveness of our proposed method, with which we can investigate contact effects and circumvent the influences of characteristic variations in OTFT fabrication.

A Planar type EEPROM cell structure which consists of adjacently placed a NMOS and a PMOS transistors with an electrically isolated common polysilicon gate by standard CMOS process (no ultra thin oxideso staclung of floating and control gates) is developed. 5 to 10 volts shifts of threshold and more than thousands cycles of endurance is obtahed.This EEPROM cell can be easily integrated with Gate Array, Standard Cell,Microprocessor LSIs. This can store Analog data and be applied to Neural chips.,