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Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

The ever increasing demand in VLSI architecture to handle complex systems has resulted for designing of high speed divider architecture. The divider is designed using ever known ancient methodology "Vedic mathematics". There are several methods present in Vedic mathematics but here Parvartya sutra is used. It is a general division formula which can be applicable to all cases of division which is an efficient way for dividing large numbers with respect to delay and power consumption. Here thirty-two bit divider architecture is implemented using this sutra & synthesized and simulated using Xilinx ISE simulator and implemented on virtex4 FPGA device XC4VLX15.The output parameters such as propagation delay and device utilization are calculated from synthesis results. Our result shows speed improvement as compared to other architecture presented in this literature. This architecture can be implemented in many applications such as digital signal processing, cryptography, processor arithmetic unit design etc.

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