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The advancements in the VLSI regime at lower technology node necessitate robust circuit design. Schmitt trigger design using domino logic style exhibit better hysteresis, higher noise margin, and reduced power consumption while compared to static CMOS Schmitt trigger design. This paper proposes three different Schmitt trigger designs based on domino logic style which produces a stable output with increased robustness against noise. The evaluation of dynamic logic-based Schmitt trigger using only NMOS transistors makes high speed operation feasible with reduced power consumption and increased hysteresis. The design, simulation, and analysis of the circuits are performed using Cadence Virtuoso using GPDK 180 nm technology library.

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