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This paper presents an efficient area and power multiplication part of radix-2 FFT (Fast Fourier Transform) architecture. The butterfly plays a central role in the FFT computation, and the multiplication part dominates its complexity. It is composed by a product of complex data and complex coefficients named twiddle factors. The proposed strategy consists on the decomposition of the real and imaginary coefficients of the twiddle factors into less complex ones, so that the multiplication part of the butterfly can be implemented with less area, what leads to the reduction of its power consumption. The strategy also includes the use of Constant Matrix Multiplication (CMM) and gate level approaches in the decomposed coefficients. A control unit is responsible for selecting the correct constant to be used after the decomposition. The proposed architectures were synthesized using SYNOPSYS Design Compiler and the UMC130nm technology. The results show that reductions of 10% in area and 8% in power could be achieved on average, when compared with state of the art solutions

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