No abstract

Diffusion furnaces in semiconductor manufacturing processes are used to grow oxide on silicon wafer surfaces or diffuse dopants into semiconductor wafers. During such process, the silicon wafers are heated in furnaces to temperatures typically in the range between 973K to 1523K. In this study, a two-dimensional axisymmetric model is employed to simulate the vertical furnace that operates at temperature 1123K. The simulation results on profile temperature distribution of a baseline case having 175 silicon wafers with diameter size of 200mm in a process tube are in good agreement with that of experimental data. The experimental data gained from furnace which was heated at 1123K is employed as a benchmark for this numerical assessment. It is also shown that uniform heating can be applied on the bulk region of the stacked wafers. In this study, the influences of heater temperature and the gap between wafers arranged in the process tube on temperature field in the process tube have been explored. From the simulations, it is worth highlighting that the temperature distribution over the bulk region of the stacked wafers is in accordance with heater temperature. In addition to that, it is found that annealing process over lesser number of wafers (with larger wafer gaps) in the boat may not significantly affects the heating performance in the furnace.