Design of a low power Successive Approximation

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This paper describes the designing of a Low Voltage, Low Dropout (LVLD) Regulator with fast self-reacting (FSR) technique in 0.18 µm CMOS process. The LVLD Regulator provides 1.2 V regulated output voltage. The design procedure includes pass transistor, error amplifier, fast self-reacting path and bandgap reference (BGR) circuit. The pass transistor is designed for a desired minimum dropout voltage. The error amplifier has been developed with a gain of 65 dB and UGB of atleast 1 MHz. Curvature compensated CMOS BGR with 1.8 V supply has been developed to produce 0.8 V output voltage with better temperature coefficient.