This paper addresses the specification and verification of hardware interface behaviors using an algebra of communicating timing charts (ACTC for short) whose underlying user model is the well known timing diagram. Terms modeling hierarchical timing charts are built in two steps. First, basic terms corresponding to the leaf charts are built, and then hierarchical terms are constructed using hierarchical operators. The basic terms model elementary behaviors as observed at the interface, and the hierarchical terms allow modeling behaviors at a higher level of abstraction: e.g., modeling an exception handling mechanism. We define an equivalence relation over the chart terms which is preserved by all the language constructs, and give a strategy to decide whether two deadlock-free basic terms are equivalent.
@IRO UMontrenl CA Re'sumt;--Cet article porte sur la specification et I'analyse comportementale des systemes temporisCs. D'abord now donnons une sCmantique fonnelle a un langage de chronogrammes. Puis, nous dkfinissonis une prockdure de passage vers un mod& intermkdiaire sur lequel l'analyse de propriktes temporelles est decidable. S . Yo\inr. "Lour11 Kronos: msnurl d'utilinnrion". L'snmng. I994 '44i TCTL: logique temporelle arborescente temporiske F. On indexe .vi ? I panir du plus grand indice des horloges de U dam T(r).
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