The implementation of cryptography algorithms is constantly observing threat from multiple techniques in breaking secure system. The current trend in breaking the secure system of cryptography is by power analysis technique. In order to break the secure key, the energy consumed in the digital circuit during computation is measured. This technique is commonly known as differential power analysis, explored by the hackers to break the secure systems. To circumvent these type of attacks, it is necessary to explore different designs, which dissipate less energy. Ideally, reversible circuits dissipate zero energy. We present a new reversible architecture for greatest common divisor (GCD) computation using modified Binary GCD algorithm. We present the generalized design methodology of reversible GCD computation unit. We compare the proposed GCD computation design with the existing design. The proposed reversible GCD architecture takes less number of iterations compared with the existing GCD architecture in the literature. The proposed design outperforms the existing GCD design in terms of Quantum Cost, Gate Count, and Ancilla Inputs. Copyright DESIGN OF GCD COMPUTATION UNITS FOR CRYPTOGRAPHY 243 principle, it is noted that [5] suppose a computer (irreversible) erases a single bit of information, the amount of energy dissipated into the environment is at least K B Tln2 (K B is Boltzmann's constant and T is temperature of the environment of the computer) per logic operation. On the other hand, Moore's principle states that the number of transistors in a chip will get doubled in every 18 months; therefore, if Moore's principle is continued to be followed in the chip design with irreversible gates, the amount of heat dissipation will increase. As a boon to solve this problem, researcher Bennett [6] from IBM introduced the idea of reversible computation to circumvent the power dissipation problem in irreversible computation. In reversible logic, inputs can be recovered from the outputs because of the unique oneto-one mapping that exists between the inputs and the outputs. The work presented in [7] shows that constructing key-dependent reversible logical circuits is not only suitable for data scrambling functions but can also be used for constructing a new general type of hardware-oriented block ciphers as well as the required key expansion algorithms. In addition, the resulting hardware designs can efficiently be protected against power analysis attack by a masking technique on the logical gate level. The reversible circuit of GCD computation unit finds application in crypto algorithms implementation using reversible logic gates. The application of GCD computation block is well demonstrated for digital video transcoding methodology discussed in [8], mixed mode and paired cipher text cryptographic algorithm for effective key distribution in [9]. The work presented in [10] aims for obtaining power attack resistant circuit. To achieve this, the design is based on Montgomery powering ladder, carry save common multiplicand Montgo...

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