In order to reduce production costs of RF devices, it is important to remove bad circuits very early in the production flow. It is all the more true for dies designed to be integrated in complex systems. Thus highly efficient RF wafer testing is mandatory for those applications to prevent the loss of assembled systems due to defective RF dies. The problem is that current RF probing technologies hardly fulfill the industrial test requirements in terms of accuracy, reliability and cost. The proposed method proves to be a very interesting alternative to validate RF parameters with no need of expensive RF equipments (RF probes and RF automated test equipments (ATE)). A new test strategy based on DC or very low frequency (LF) measurements, which allows the elimination of expensive RF tests, is presented. The main idea is to insert some simple design for test (DfT) circuitry within the chip.This DfT provides relevant information on the structural behavior of the device blocks. The internal node data are additional to standard DC test measurements like power supply current or advanced DC test signatures (e.g. Vdd ramping), and LF measurements like gain in loopback mode.Since RF performance of each block is directly related to such structural data, it is possible to predict the RF characteristics of the blocks without time consuming RF measurements. RF parameters estimation is performed using nonlinear Artificial Neural Networks.