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The paper focuses on implementation of several different concepts of wise analysis of light electric vehicle propulsion unit testing facility. Firstly, the concept of "digital twin" that represents a simulated replica of a complete testing facility is presented. More, instead of using an off-line simulation environment, the digital twin (DT) is programmed to run using two field programmable gate arrays (FPGA), hence it becomes an online real-time simulation. The second concept is the distribution of the digital twin. The actual unit controller is programed into one FPGA and the machine under test, its load and the power inverter are implemented into a second FPGA. The communication between the two is handled using analog and digital lines, just like the controller would be connected to the real test-bench. The third concept involves the organization of each of the two FPGA programs, based on Energetic Macroscopic Representation (EMR) that facilitates transparency, ease of implementation and minimizes the error in coding the actual test-bench replica and then its controller. Combining all the above mentioned concept into one single lucrative tool, experimentally validated by actual measurements, proves that the concept of using a DT implemented in real-time, without doubt can be used for testing prototypes and their controls regardless of the actual test-bench. Hence, on one hand it is eco-friendly, precise and save testing method and on the other hand, the same DT can be used by researchers and testers in facilities that do not have a test-bench at their disposal.

The present paper proposes a genuine, simple to implement, robust and reliable method for current sensors fault detection and compensation used for 3-phase inverters. Its functionality is based on an algorithm programed into a Field Programmable Gate Array (FPGA) as general controller. Usually, 3-phase inverters are controlled using field oriented control (FOC) which is generally triggered to sample the measured currents on the established switching frequency. As the latter is much smaller than the base clock of the FPGA, this allows hundreds of free time samples to perform other calculations in-between two FOC samplings. In this paper, a method that uses these free and unused time samples is presented. This method performs calculations for fault detection and compensation ensuring that at each new FOC sampling, this will receive the correct current data to reach continuous operation despite faults. The interleaving principle of the FOC with the fault detection method, as it will be proven in the paper, ensures high reliability of the complete controller diminishing the possibility of undesired or faulted readings to disturb the FOC's calculations. The fault detection philosophy is based on continuous comparison of the instantaneous measured currents (sensor's response) against reference values. The experimental results presented in the paper prove reliable operational performances of the method in both steady state and transient conditions. The added value of the paper consists in its genuine approach to handle the fault detection and compensation in-between two PWM ticks, ensuring that no faulted measurements can reach the control unit. This added value is based on functionality divided on several functions triggered by an internal generated clock synchronizing and handshaking their operations towards one goal: fault detection and compensation. INDEX TERMS Electrical fault detection, fault tolerant control, fault diagnosis.