No abstract

The logic construction of a double-edge-triggered (DET) flipflop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other existing CMOS DET flip flops. By simulating and comparing the proposed DET flip-flop with the other designs present, it is shown that the proposed DET flip-flop reduces power dissipation while keeping the same date rate and can be used for high speed applications.

The novel 4T Design(1), though efficient, has several parasitic effects of 1 st Generation accumulated in it. These parasitic effects are discussed in this paper. After testing the prototype, it was observed that effects like body effect, drain actuation etc. are still present in the system. This paper discussed them all and provides a key to solve the issues rising from these effects.

The article that you are looking for is unavailable to public domain. The article is subjected to compliance with 2014-2015 IJCA scientific data guidelines. You might want to navigate the journal via the menu options provided in the left side of the screen. However, feel free to contact us anytime regarding any article which you are unable to find.