In this paper, we achieved excellent variation control, endurance enhancement, and leakage reduction in zirconium (Zr)-doped hafnium oxide (Hf 1−x Zr x O 2 ) based ferroelectric films by the germination of large ferroelectric grains through extending the duration of rapid thermal annealing without increasing the temperature beyond 700 °C. The pivotal point of this work is to reduce electrical variations in ferroelectric capacitors, which we attribute to the random variation in ferroelectric and dielectric phases. The motivation for this research originally stemmed from Johnson− Mehl−Avrami−Kolmogorov's theory of nucleation, which predicts that a sufficient time is required for forming any particular phase during phase transformation. Instead of increasing the temperature beyond 700 °C, extending the duration of rapid thermal annealing allows uniform crystal to form, which agrees with the theory. A 10 nm thick Hf 1−x Zr x O 2 film (x = 0.2) has been fabricated. The duration and temperature of rapid thermal annealing (RTA) under a nitrogen (N 2 ) atmosphere at 1 atmospheric pressure (atm) is varied to observe its effect on crystal formation and the electrical properties of the devices. It was observed that very low temperature and short (30 s) duration annealing at 1 atm pressure cannot infuse ferroelectricity in Hf 1−x Zr x O 2 . Structural analysis clearly showed the formation of large and uniform ferroelectric domains with negligible impact on surface roughness upon extending the annealing duration up to 180 s. The device-to-device variation in terms of standard deviation of coercive voltage and peak capacitance are reduced from 400 to 17 mV and from 20 to 4 fF/cm 2 , respectively, by increasing the RTA duration at 700 °C. The devices have also displayed endurance above 1 million cycles and leakage current density below 10 pA/μm 2 . The simple physics-based process discussed here reduces the thermal budget required for Hf 1−x Zr x O 2 , mitigates the randomness in the domain distribution, and infuses deterministic switching. This improvement paves the way for implementing Hf 1−x Zr x O 2 -based, deeply scaled ferroelectric devices for memory and steep slope device applications.

This work presents 2-bits/cell operation in deeply scaled ferroelectric finFETs (Fe-finFET) with a 1 µs write pulse of maximum ±5 V amplitude and WRITE endurance above 109 cycles. Fe-finFET devices with single and multiple fins have been fabricated on an SOI wafer using a gate first process, with gate lengths down to 70 nm and fin width 20 nm. Extrapolated retention above 10 years also ensures stable inference operation for 10 years without any need for re-training. Statistical modeling of device-to-device and cycle-to-cycle variation is performed based on measured data and applied to neural network simulations using the CIMulator software platform. Stochastic device-to-device variation is mainly compensated during online training and has virtually no impact on training accuracy. On the other hand, stochastic cycle-to-cycle threshold voltage variation up to 400 mV can be tolerated for MNIST handwritten digits recognition. A substantial inference accuracy drop with systematic retention degradation was observed in analog neural networks. However, quaternary neural networks (QNNs) and binary neural networks (BNNs) with Fe-finFETs as synaptic devices demonstrated excellent immunity toward the cumulative impact of stochastic and systematic variations.

This paper reports 2bits/cell ferroelectric FET (FeFET) devices with 500 ns write pulse of maximum amplitude 4.5V for inference-engine applications. FeFET devices were fabricated using GlobalFoundries 28nm high-k-metal-gate (HKMG) process flow on a 300mm wafer. The devices were characterized, and statistical modeling of variations in the fabricated devices was carried out based on experimental data. Furthermore, the model was applied to multi-layer perceptron (MLP) neural network (NN) simulations using the CIMulator software platform. The neural network (NN) was trained offline, and the weights were transferred to the synaptic devices for an inference-only operation. Device-to-device (D2D) and cycle-tocycle (C2C) variations are limited by optimal process conditions and do not impact inference accuracy. However, due to short-term retention, read-to-read (R2R) variation significantly affects inference operation. This work proposes a synergistic READoptimization approach to mitigate the impact of short-term retention and device variation issues. The optimization technique fostered immunity in the MLP-NN towards R2R variations, and the MLP-NN maintains inference accuracy of 97.01%, while the software baseline is 98%.