Resistive Computation was suggested by [6] as an idea for tacking the power wall by replacing conventional CMOS logic with Magnetic Tunnel Junction (MTJ) based Look-Up Tables (LUTs). Spin Transfer Torque RAM (STTRAM) is an emerging CMOS-compatible non-volatile memory technology based on Magnetic Tunnel Junctions as a memory bit [3]. The principal advantage of STTRAM is that it is leakage-resistant, which is an important characteristic beyond the 45nm technology node, where leakage concerns are becoming a limiting factor in microprocessor performance. Although STTRAM is a good candidate for replacing SRAM for on-chip memory, we argue in this article MTJ-based LUTs are unnecessarily expensive in terms of area, power, and performance when implementing fixed combinational logic that does not require the reprogramming ability provided by MTJs.

Semiconductor technology has been scaling at a steady pace following Moore's law. The current generations of the technology have reached dimensions well below 100nm where nano-scale phenomena are prominent. Transistors in such a small scale behave very differently than the classic long channel devices taught in most undergraduate level textbooks. Moreover, there are new challenges in nano-scale circuit design, such as process variations and reliability issues that are not taught in undergraduate level courses. Working on latest technology issues is typically an opportunity available only to graduate level students working on related research projects. To address this gap, using a NASA Curriculum Improvements Partnership Award for the Integration of Research (CIPAIR) grant, we have created a summer internship program that engages community college students in research projects on the latest challenges of circuit design in nano-scale semiconductor technology. Through this program, four community college students were mentored by two graduate students in a research project to analyze performance degradation of integrated circuits due to transistor aging effects in nanoscale. In this research, analysis of transistor breakdown was performed through computer simulations to understand effects on circuit power and performance. A ring oscillator circuit was utilized as a generic logic circuit for this research. The breakdown was modeled by resistors placed between the transistor terminals. The value of the resistor represents the severity of the breakdown; large resistors represent fresh transistors, whereas low resistors represent a fully broken transistor. In addition to computer simulations, real ICs were studied by taking power measurements experimentally. This research aims to offer better insight into the impact of transistor breakdown and to improve IC design in nano-scale. Through this internship program, the undergraduate students not only contributed to research and discovery, but also gained valuable experience and knowledge of nano-scale circuits that could have not been achieved in traditional educational methods.