In this work, a bus encoding method is proposed that reduces the effect of crosstalk. The crosstalk usually occurs when the data is in parallel communicated. In planar structures, the crosstalk effect is large due to the usage of parallel communication and wide data patterns. In bus technique, the huge amount of wires is laid in equal over a significant time. One way to reduce crosstalk without changing the parallel communicating data lines is to reduce the wideband data patterns so as to reduce the power utilization. The proposed encoding method can minimize the crosstalk by reducing wide data patterns without degrading the performance. The architecture is implemented on Artix 7 FPGA at a 28nm technology node. The simulation is done using the HDL tool and the results are compared with the existing FPGA architecture. With the proposed method, the wire density and the power consumption are reduced by 57.4% and 50% respectively as compared with existing 45 nm technologies.