A bilateral filter for image processing is implemented on synchronous field programmable gate array. The reason for selecting bilateral filter is that it reduces noise while maintaining the details of the image and the design of bilateral filter is described on register transfer level. Our design concept consists of changing the clock domain in such a way that only one pixel clock cycle is required for the processing of the entire filter window i.e, kernel-based processing is performed. The main purpose of this kernel-based design is that it divides the input data into groups so that the internal clock of the design is a multiple of the pixel clock. Finally, the difficulty of the design is mostly reduced by making use of the separability and regularity of one filter component. By utilizing the dedicated resources effectively and economically the bilateral filter is implemented as highly parallelized pipeline structure. With low effort different sizes of kernels can be implemented because of the modularity of the filter design. Negligible quality loss of the output image is obtained due to the quantization of filter coefficients.

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