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Application development with hardware description languages (HDLs) such as VHDL or Verilog involves numerous productivity challenges, limiting the potential impact of reconfigurable computing (RC) with FPGAs in highperformance computing. Major challenges with HDL design include steep learning curves, large and complex codes, long compilation times, and lack of development standards across platforms. A relative newcomer to RC, the Open Computing Language (OpenCL) reduces productivity hurdles by providing a platform-independent, C-based programming language. In this study, we conduct a performance and productivity comparison between three image-processing kernels (Canny edge detector, Sobel filter, and SURF feature-extractor) developed using Altera's SDK for OpenCL and traditional VHDL. Our results show that VHDL designs achieved a more efficient use of resources (59% to 70% less logic), however, both OpenCL and VHDL designs resulted in similar timing constraints (255MHz < fmax < 325MHz). Furthermore, we observed a 6× increase in productivity when using OpenCL development tools, as well as the ability to efficiently port the same OpenCL designs without change to three different RC platforms, with similar performance in terms of frequency and resource utilization.

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Two of the most critical tasks when designing a portable wireless neural recording system are to limit power consumption and to efficiently use the limited bandwidth. It is known that for most wireless devices the majority of power is consumed by the wireless transmitter and it often represents the bottleneck of the overall design. This paper compares two compression techniques that take advantage of the sparseness of the neural spikes in neural recordings using an information theoretic formalism to enhance the well-established vector quantization (VQ) algorithm. The two discriminative VQ algorithms are applied to neuronal recordings proving their ability to accurately reconstruct action potential (AP) regions of the neuronal signal while compressing background activity without using thresholds. The two operational modes presented offer distinct characteristics to lossy compression. The first approach requires no preprocessing or prior knowledge of the signal while the second requires a training set of spikes to obtain AP templates. The compression algorithms are implemented on an on-board digital signal processor (DSP) and results show that power consumption is decreased while the bandwidth is more efficiently utilized. The compression algorithms have been tested in real time on a hardware platform (PICO DSP ) enhanced with the DSP which runs the algorithm before sending the compressed data to a wireless transmitter. The compression ratios obtained range from 70:1 and 40:1 depending on the signal to noise ratio (SNR) of the input signal. The spike sorting accuracy in the reconstructed data is 95% compatible to the original neural data.

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