This paper investigates the possibility of creating an energy profile of a RISC processor instruction set in the prototyping phase, using FPGA implementation and physical measurements. In order to determine the power consumption at instruction-level, several programs have been developed and run on the processor implementation on FPGA. The experiments have focused at the following groups of instructions: arithmetic and logic (ALU) instructions, memory access instructions, control instructions, compare and move instructions. The main goal of our work is the investigation of the correlation between dynamic power consumption of a RISC processor design implemented in different technologies (FPGA vs. ASIC) and manufacturing processes, called power technology gap. The achieved correlation coefficient between the FPGA 45nm physical power measurements and ASIC 45nm power estimation is 86.39%.

This paper investigates the possibility of energy profiling for FPGA based designs by means of direct board based measurement. We aim to determine how different design parameters and FPGA components usage affect the overall power and energy consumption of the device. The power and energy measurements have been performed on a Digilent Atlys board with Xilinx Spartan-6 device. We have varied the following parameters: the usage of slice-based resources, the usage of DSP block, the usage of BRAM memory modules and the clock frequency. Our goal is represented by the development of an accurate energy profiling methodology which will enable to estimate the power consumption of FPGA designs.