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In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP.

Pulsed bias is an attempt to improve the performance of oscillators in integrated circuits as a result of architectural innovation. Given the relatively low value of resonator quality factor achievable on-chip, for a specified bias voltage level, pulsed bias may result in a lower power consumption and in an improvement of the spectral purity of the oscillation. The main drawback of this approach is the need to introduce a certain time delay in order to properly position pulses with respect to oscillation waveform. Delay accumulation requires further energy dissipation and introduce additional jitter. In this paper we present a new architecture capable to avoid unnecessary delay, based on the idea to apply the pulsed bias approach to a quadrature oscillator. A ?rst circuit-level implementation of this concept is presented with simulation results

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