After producing a chip, the functional correctness of the integrated circuit has to be checked. Otherwise, products with malfunctions would be delivered to customers, which is not acceptable for any company. During this post-production test, input stimuli are applied and the correctness of the output response is monitored. These input stimuli are called test patterns. Many algorithms for Automatic Test Pattern Generation (ATPG) have been proposed in the last 30 years. However, due to the ever increasing design complexity, new techniques have to be developed that can cope with today's circuits.Classical approaches are based on backtracking over the circuit structure. They have been continuously improved by using dedicated data structures and adding more sophisticated techniques like simplification and learning. Approaches based on Boolean Satisfiability (SAT) have been proposed since the early 1980s. Comparisons to other "classical" approaches based on FAN, PODEM and the D-algorithm have shown the robustness and effectiveness of SAT-based techniques.Recently, there is a renewed interest in SAT, and many improvements to proof engines have been proposed. SAT solvers make use of learning and implication procedures. These new proof techniques led to breakthroughs in several applications, like formal hardware verification.In this book, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation of this problem as a SAT problem is considered. Modern SAT solvers are explained and the transformation of ATPG to SAT is discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, use of various fault models and v vi PREFACE detailed experiments on multi-million gate designs. The book describes the state-of-the-art in the field, highlights research aspects and shows directions for future work.

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Test compaction is an important aspect in the postproduction test since it is able to reduce the test data and the test costs, respectively. Current ATPG methods treat all faults independently from each other which limits the test compaction capability. This paper proposes a new optimization based SAT-ATPG for compact test set generation. Robust solving algorithms are leveraged to determine fault groups which can be detected by the same test. The proposed technique can be used during initial compact test generation as well as a post-process to increase the compactness of existing test sets, e.g. generated by commercial tools, in an iterative manner. Experimental results on industrial circuits and academic benchmarks show that this technique is able to significantly reduce the pattern count down to 40% for the initial test generation and down to 30% for the iterative reduction.

As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to detect small delay defects and to verify the correct temporal behavior of a circuit.In this article, MONSOON, an efficient SAT-based approach for generating non-robust and robust test patterns for path delay faults is presented. MONSOON handles tri-state elements and environmental constraints occurring in industrial practice using multiple-valued logics. Structural techniques increase the efficiency of the algorithm. A comparison with a state-of-the-art approach shows a significant speed-up. Experimental results for large industrial circuits demonstrates the feasibility and robustness of MONSOON.