Many high-speed communication applications require precise edge-control for establishing ideal sampling conditions. A delay-locked loop (DLL) is often used to phase shift the incoming reference clock signal in increments of the propagation delay of a single inverter circuit.Through the application of sigma-delta modulation techniques, this paper will demonstrate how a DLL can be used to provide precise edge control with sub-gate-delay resolution.

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An instrument for on-chip measurement of transceiver transmission capability is described that is fully realizable in CMOS technology and embeddable within an SoC. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. At the core of this work is the use of ΣΔ amplitude-and phase-encoding techniques to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. The same technique is also used for generating the test stimulant for the device-under-test.cloud computing, etc. In order to keep component costs down, low-cost test techniques are essential. One strategy is to incorporate test circuits directly on-chip to standardize test equipment access, improve accuracy and repeatability, and to contribute to short test times through parallel test procedures. In some cases, an on-chip instrument may be the only means to capture information associated with some internal core circuit. An important attribute of such on-chip test circuits is a low silicon area overhead. In addition, such on-chip instruments are not bandwidth limited by the test channel, so tests can be performed at the desired operating frequencies and speeds [7]. A software programmable, probabilistic test instrument using ΣΔ-encoded phase/amplitude-signal generators is to be described in this paper.This work in a shorter form was first presented at the 20th International Mixed-Signal Testing Workshop [14]. In that publication the general concept of the probabilistic instrument was proposed and demonstrated with discrete components. In this publication, our first attempt at integrating the concept into a 130 nm CMOS IC realization. The results of this endeavor will also be described here. While our intent is to use this instrument as part of an embedded instrument for high-speed transceivers, however, at this point in time, the IC results do not operate anywhere close to the 1 Gbps rates required by today's I/Os. This is not meant to be a definitive statement that the approach is not sound but rather the results gather here is a testament of the working principle. It is expected that future work will improve the operating speed and measurement resolution suitable for next generation transceiver ICs. This paper will begin with a system overview of the probabilistic test instrument (PTI) in Section II, including a description of various methods for phase and voltage signal generation using sigma-delta encoding methods, and CDF extraction. Section III will describe the critical decision-making circuits such as the D-type flip-flops and comparator circuits used in the CMOS IC implementation. Section IV will describe the Responsible Editors: