In this paper, we developed an isotropic wet etching process in a capsule-type bevel etch chamber to reduce a Cu overburden of through Si via (TSV) for less wafer-level warpage with 300 mm wafers. We report the relationship between the wafer-level warpage and the Cu overburden thicknesses controlled by the isotropic wet etching with diluted solution of hydrogen peroxide and sulfuric acid, which is widely used for Cu wet etching. After Cu filling by electroplating, there are humps at the top of the TSVs; therefore, the isotropic wet etching can be considered as a solution to etch away the Cu overburden without any damages on the TSVs. We modified the capsule-type bevel etch chamber to avoid serious attack on TSVs at the center area of the wafer caused by the etchant delivery path. We also adjusted the process parameters to have a controllable Cu etch rate. The etch rate of ∼0.2 µm/s and the uniformity of ∼3% were achieved. The overburden was able to be etched up to 3 µm from the initial Cu overburden. While the Cu overburden decreased during the isotropic wet etching, the TSVs were protected from the etchant because of the humps at the top of the TSVs. After the Cu electroplating, there was a grain size difference between the Cu at TSV and the Cu at field area. Because the microstructural difference caused a galvanic corrosion during the wet etching, the etch rate of the adjacent Cu around TSV was faster than the Cu at any other area. That resulted in exposure of dielectric layer at the adjacent area around TSVs when the Cu overburden was etched heavily. It may be another protection mechanism of TSV during the isotropic wet etching. The wafer-level warpage of the wafer with the Cu overburden etched up to 3 µm after the annealing decreased by 50% from that of the wafer with the initial Cu overburden. The wafer-level warpage exhibited a linear relationship with the Cu overburden thickness controlled by the isotropic wet etching.Index Terms-Cu filling, Cu overburden, galvanic corrosion, isotropic wet etch, microstructure of Cu, through Si via (TSV), wafer warpage, wafer-level packaging. publication by Associate Editor B. Dang upon evaluation of reviewers' comments.The authors are with the Institute

Various types of polyimide have been used widely in the manufacturing of integrated circuits and MEMS’ (Micro Electrical Mechanical Systems) such as sensors. These organic spin-on polymers exhibit a wide range of mechanical and electrical properties and have been commonly used for electrical insulation as well as device passivation and protection. In addition, these organic spin-on polymers serve as excellent sacrificial materials for forming cavities on MEMS structures. This work studies the gapfill properties of several polyimides after spin-coating and curing. In addition, this work examines and compares the gapfilling and planarization properties of a number of different polyimides, including multiple layers of polyimides for gapfilling and planarization.

A new generation of negative tone and chemically amplified positive tone photoresists by TOK, JSR, Dow Chemical and others has gained momentum for advanced packaging applications. Resist thickness requirements are increasing to the 40-100 μm range as Cu pillars and micro-bumps are adopted, to accommodate the tighter pitches required in the newest multi-chip package designs. In order to form the pillars, the resist mask must be thicker than the height of the pillars to contain the entire bump structure.

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