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This paper presents power and area optimized, high-speed metal-oxidesemiconductor (MOS) current mode logic (MCML)-based frequency dividers. Each differential pair in the divider is sized separately to minimize the overall power consumption. The divide-by-2 frequency divider has been realized in a 180-nm complementary MOS (CMOS) process technology, and postlayout simulation results show that the proposed frequency divider can work up to an operating frequency of 18.8 GHz in the worst-case process corner with a maximum power dissipation of 1.715 mW under 1.8-V supply. It gives a bandwidth of 19.9 GHz which ranges from 1 to 20.9 GHz. The divider occupies a 0.106 Â 0.09 mm 2 area. The performance corresponds to the figure of merit (FoM) of 43.61 dB. The same optimized latches and two EX-OR gates are used to design a divide-by-5 frequency divider that is also realized in 180-nm CMOS process technology. The postlayout simulation results show that the proposed divide-by-5 frequency divider can faithfully work up to an operating frequency of 12.12 GHz in worst-case process corner with an excellent power head performance. The maximum power dissipation of the core circuit is 1.39 mW under 1.8-V supply. It occupies a 0.166 Â 0.116 mm 2 area. The performance corresponds to the FoM of 26.56 dB which compares favorably with the state of the art.

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