No abstract

Chaotic systems plays a vital role in the field of security, data hiding and steganography. FPGA implementation makes more advantageous compared to analog one. Different chaotic systems like chaos generator and nondeterministic number generator used for security purpose and key generation were successfully realized in FPGA. In this paper, FPGA implementation of Pandey-Baghel-Singh chaotic system (PBSCS) using Euler and RK4 numerical algorithms is presented. Pandey-Baghel-Singh chaotic system were obtained using numerical differential solution and numerically modelled in Verilog with the environment of Xilinx Vivado 2017.3 design suite. The design is verified using experimental setup with the help of interfacing to PC and FPGA family of Artix-7 Nexys 4 DDR and Basys3. Performance of the FPGA based chaotic generator using Euler and RK4 algorithm are analyzed using 1 GB data sets with the maximum operating frequency achieved up to 359.71 MH