Antibody detection by serological methods gained a lot of interest in recent years and has become the backbone of virological diagnosis. Despite the detection of all five classes of immunoglobulins in urine, not much attention has been paid to the use of urine as a diagnostic sample to detect viral antibodies. Unlike venipuncture, this non-invasive mode of sample collection can help cover all age groups, especially paediatric and old age patients, where blood collection is difficult. Using urine as a sample is also economical and involves lesser risk in sample collection. The antibodies are found to be stable in urine at room temperature for a prolonged period, which makes the sample transport management easier as well. A few recent studies, have also shown that the detection limit of antibodies in urine is at par with serum or other clinical material. So, the ease in sample collection, availability of samples in large quantity and stability of immunoglobulins in urine for prolonged periods can make urine an ideal sample for viral diagnosis.

New complex and Low Power systems are being implemented using advanced Electronic Design Automation (EDA) tools. Low power designs are not only used in small size applications like mobile phones, tablets and handheld devices but also in high-performance computing applications. As the complexity increases day by day, the dissipation of power has emerged as one of the very important design constraints. In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the Flip-Flop is an important element to determine the performance of the synchronous circuit. In the research of low power and low voltage VLSI circuits, the use and implementation of Dual Edge Triggered Flip-Flop (DETFF) has gained more attention at the gate level design. The main advantage of using DETFF is that it allows one to maintain a constant throughput while operating at only half the clock frequency. In this paper, a dual-edge triggered sense amplifier flip-flop is designed for low power systems. For DETFF, the optimal delay, power consumption, and energy are determined as the primary figures of merit. The use of dual edgetriggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed.

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