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In biomedical implants, the RF transceivers require the low power and less size components for acquiring best results in frequency and phase controlling. The RF transceivers obtain the information from either sides of sources in biomedical applications. Access the signal from human body and processed it through amplifiers, Phase Locked Loops (PLLs), mixers & filters and many more for controlling the parameters. Majorly the PPLs provide the required frequency for the entire operation to obtain this All Digital Phase Locked Loop (ADPLL) is mostly used. In ADPLL, DCO is a major block through which fine frequency resolution is achieved. The present project concentrates on designing the low power Digitally Controlled Oscillator (DCO).

Chronic diseases and rising aging populations are the major reasons towards the usage of low power, low noise, life time performance Biomedical Implantable Devices. Efficient architectural designs will be responsible for the requirements set out above. This paper focuses on the ADPLL DPFD architecture for implantable biomedical devices. For high performance DPFD, the dead zone, lock in time is a seldom limitation to ADPLLs. In the present paper, a new approach to design a dead zone free with fast and high locking time and low phase noise DPFD is considered to be a challenge. This can be accomplished by carefully controlling the reference and feedback clock frequencies of the phase detector with the proposed NIKSTRO/SURAV latch based sense amplifier. The proposed architecture was developed and simulated using 45nm technology and it is observed that it provides a 20ns dead zone with 4.8mW of power consumption at the rate of 1.8GHz, while the lock in time for the proposed method is 340ns with moderate phase noise. It is also noted that the designed one showed better results when compared to the existing ones.

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Recent IC technology innovations can achieve lowpowe r biomedical implant functionality.RF transceivers require low-power and small-sized components in biomedical implants to achieve the best results in frequency and phase control. Phase Locked Loop (PLL) is the key component for controlling these parameters in low power consumption RF transceivers. Therefore All Digital Phase Locked Loop (ADPLL) is chipping effectively into a major role in the fields of Biomedical & Communication. ADPLLs contribute better results in these areas due to their efficient blocks. This paper focuses on the design of low-power Digital Controlled Oscillator (DCO) and provides information on the various ADPLL blocks. To reduce power dissipation DCO is designed with XNOR gate using delay elements by avoiding direct contact between VDD & GND and the MOS transistors were arranged in ring topology. Tanner tools were used to design and simulation. In addition to this it also provides the detailed history of PLLs & ADPLLs and their mathematical analysis. Compared to previous design, the current DCO design gives better power consumption results.