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Resistivity difference between Cu wires made with plating using high purity ͑new plating process͒ and conventional purity ͑conventional process͒ materials has been evaluated in order to develop the process for the realization of high performance LSIs. This resistivity difference is relatively small, i.e., 8% when line width is wide ͑200 nm͒. However, it increases with the decrease in line width, and it reaches about 20%, i.e., 2.8 ⍀ cm for the former and 3.5 ⍀ cm for the latter at 50 nm line width. A 50 nm wide Cu wire formed with the new plating process had more uniform and larger grain sizes and lower impurity concentrations than the wire formed with the conventional process.Copper has been used as an interconnect material for high performance ultralarge scale integrations ͑ULSIs͒ due to its low electrical resistivity and high reliability. However, the resistivity of Cu interconnects increases significantly with a decreasing line width of less than 100 nm. 1-4 This is becoming a critical issue for the realization of high speed ULSIs, and it is mainly because the line widths are comparable to the mean free path of the electron ͑40 nm͒; hence, electron scattering occurs at the grain boundaries, resulting in the higher resistivity of very narrow Cu wires. 5 To lower the resistivity, both the coarsening of the grain sizes and reduction of the thickness of high resistivity barrier metals in Cu wires are very important. Self-forming barriers using Cu-Mn or Cu-Ti alloys and atomic layer deposition are possible candidates to promote the formation of thinner barriers. 6,7 The most effective method to reduce Cu wire resistivity is to lower the resistivity of the Cu wires themselves by coarsening the grain sizes. It has been recently reported that impurities such as oxygen, sulfur, and nitrogen concentrate on the grain boundaries of Cu wires and depress their grain growth during annealing. 8,9 These results imply that low resistivity Cu wires can be formed if high purity, very narrow Cu wires can be formed.Hence, we focused our attention on the purification of Cu wires using a newly developed nominal high purity 9N anode and nominal high purity 6N-CuSO 4 ·5H 2 O electrolyte ͑new plating process͒. Resistivities of Cu wires formed with the new plating process were measured and compared to those of Cu wires formed with a conventional purity 4N anode and 3N-CuSO 4 ·5H 2 O electrolyte ͑conven-tional process͒.Using the new plating process, we achieved 50 nm Cu wires with ϳ20% lower resistivity than those made by the conventional process. In this paper, we first investigated grain sizes and textures of plated films obtained using the new plating and conventional processes. Then, the resistivities of Cu wires made with the new plating process were evaluated as a function of wire width in comparison with those of Cu wires formed with the conventional process. Finally, we considered the mechanism for achieving low resistivity by evaluating the grain sizes, impurities, and lattice images of 50 nm wide Cu wires made by both the new p...

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The behavior of atoms in a solid under a strong acceleration field of around 1 million (106) g at high temperature (mega-gravity field) was examined. The ultracentrifuge experiment was performed on an antimony (Sb)-bismuth (Bi) system solid alloy in a maximum acceleration field of (0.85–1.03)×106 g at 220–240° C for 85 hours. Large composition gradients of Sb (about 20–0 wt%) and Bi (80–100 wt%) and the continuous changes in lattice parameters were observed at that location where the external energy was comparable to or larger than the thermal energy. This result provides the first evidence of the sedimentation of component atoms in a solid.

Grain size distributions and average grain sizes in the longitudinal direction of the Cu interconnect in 50-, 70-and 80-nm-wide Cu interconnects were evaluated and compared with the resistivities of each interconnect. After annealing, the standard deviation of grain sizes for 50-nm Cu interconnect increased to 27.5, and the average grain size microstructure grew to larger than that of as-deposited 50-nm Cu interconnects. The value of standard deviation of grain sizes in the normal distribution histogram for a 50-nm wire was found to be much smaller than those for 70-and 80-nm Cu wires after annealing. This implies that adequate grain growth should not be expected in the very narrow Cu interconnects (less than 50-nm) of the future if they are made with the conventional annealing process.