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A novel way of manufacturing an on-chip transformer that produces high inductance ratio (L Sec /L Pri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (Primary Coil), having large effective width, and a densely routed conductor B (Secondary Coil). Thus, a high turn ratio monolithic transformer, using minimum die size, is realizable on silicon. The coil having the dense routing can also be doubled up as a monolithic RF choke on silicon. In this work, area efficiency is compared between various type of existing transformer structures (i.e. Interleaved and Stacked transformer), based on unit inductance. The method presented is fully compatible to all the foundry standard CMOS processes.

A stacked tunable inductor with extremely high quality factor (Q) p2000) is presented. Compared with transformer-type inductors with interleaved configuration, fullwave electromagnetic (EM) simulation results demonstrate that the stacked structure offers greater advantages in terms of area efficiency, achievable inductance value, and peak Q frequency. Besides, detailed discussions on power levels at the inputs of driving coils a r e presented to illustrate the effects of parasitic capacitance between the primary coil and driving coil.

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