In

We present a concurrent testing methodology for detecting catastrophic faults in droplet-based microfluidic systems and investigate the related problems of test planning and resource optimization. We apply this methodology to a droplet-based microfluidic array that was fabricated and used to perform multiplexed glucose and lactate assays. The test approach interleaves test application with the biomedical assays and prevents resource conflicts. We show that an integer linear programming model can be used to minimize testing time for a given hardware overhead due to droplet dispensing sources and capacitive sensing circuitry. The proposed approach is therefore directed at ensuring high reliability and availability of bio-MEMS and lab-on-a-chip systems, as they are increasingly deployed for safety-critical applications.

We present a concurrent testing methodology for detecting catastrophic faults in digital microfluidics-based biochips and investigate the related problems of test planning and resource optimization. We first show that an integer linear programming model can be used to minimize testing time for a given hardware overhead, for example, droplet dispensing sources and capacitive sensing circuitry. Due to the NP-complete nature of the problem, we also develop efficient heuristic procedures to solve this optimization problem. We apply the proposed concurrent testing methodology to a droplet-based microfluidic array that was fabricated and used to perform multiplexed glucose and lactate assays. Experimental results show that the proposed test approach interleaves test application with the biomedical assays and prevents resource conflicts. The proposed method is therefore directed at ensuring high reliability and availability of bio-MEMS and lab-on-a-chip systems, as they are increasingly deployed for safety-critical applications.

We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field IntroductionAs technological trends continue to lead toward smaller device and wire dimensions in integrated circuits, the probability of hard (permanent) faults in microprocessors increases. These faults may be introduced during fabrication, as defects, or they may occur during the operational lifetime of the microprocessor. Well-known physical phenomena that lead to operational hard faults are gate oxide breakdown, electromigration, and thermal cycling. Microprocessors become more susceptible to all of these phenomena as device dimensions shrink [28], and the semiconductor industry's roadmap has identified both operational hard faults and fabrication defects (which we will collectively refer to as "hard faults") as critical challenges [13]. In the near future, it may no longer be a cost-effective strategy to discard a microprocessor with one or more hard faults, which is what, for the most part, we do today.Traditional approaches to tolerating hard faults have masked them using macro-scale redundancy, such as triple modular redundancy (TMR). TMR is an effective approach, but it incurs a 200% overhead in terms of hardware and power consumption. There are some other, lightweight approaches that use marginal amounts of redundancy to protect specific portions of the microprocessor, such as the cache [36,18] or buffers [5], but none of these are comprehensive.Our goal in this work is to create a microprocessor design that can tolerate hard faults without adding significant redundancy. The key observation, made also by previous research [25,27,29], is that modern superscalar microprocessors, particularly simultaneously multithreaded (SMT) microprocessors [32], already contain significant amounts of redundancy for purposes of exploiting ILP and enhancing performance. We want to use this redundancy to mask hard faults, at the cost of a graceful degradation in performance for microprocessors with hard faults. In this paper, we do not consider adding extra redundancy strictly for fault tolerance, because cost is such an important factor for commodity microprocessors. The viability of our approach depends only on whether, given a faulty microprocessor, being able to use it with somewhat degraded performance provides any utility over having to discard it. To achieve our goal, the microprocessor must be able to do three things while it is running.• It must detect and correct errors caused by faults (both hard and transient).• It must diagnose where a hard fault is, at the granularity of the field deconfigurable unit (FDU).• It must deconfigure a faulty FDU in order to prevent its fault from being exercised.

Recent years have seen the emergence of droplet-based microfluidic systems for safety-critical biomedical applications. In order to ensure reliability, microsystems incorporating microfluidic components must be tested adequately. In this paper, we investigate test planning and test resource optimization for droplet-based microfluidic arrays. We first formulate the test planning problem and prove that it is NP-hard. We then describe an optimization method based on integer linear programming (ILP) that yields optimal solutions. Due to the NP-hard nature of the problem, we develop heuristic approaches for optimization. Experimental results indicate that for large array sizes, the heuristic methods yield solutions that are close to provable lower bounds. These heuristics ensure scalability and low computation cost.