The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-in Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-in Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.

Food crop classification and identification are crucial aspects of modern agriculture. With progression of drones or unmanned aerial vehicles (UAVs), crop detection from RGB images goes through a paradigm shift from traditional image processing methods to deep learning (DL) methods due to effective breakthroughs in convolutional neural networks (CNN). Drone images are reliable for identifying different crops because of its higher spatial resolution. Food crop classification utilizing deep learning on drone images includes machine learning techniques for distinguishing and identifying different types of crops in images captured by UAVs. It is beneficial for various applications, like crop monitoring and precision agriculture. This paper presents a new Satin Bowerbird Optimization with deep learning for Food Crop Classification (SBODL-FCC) technique on UAV images. The presented SBODL-FCC technique exploits DL models with hyperparameter optimizers for food crop classification on UAV images. To accomplish this, the presented SBODL-FCC technique employs adaptive bilateral filtering technique for image preprocessing. Besides, the SBODL-FCC technique uses MobileNetv2 feature extractor with Bayesian optimization (BO) algorithm for parameter optimization. Moreover, the food crop classification process is performed through convolutional long short-term memory (ConvLSTM) model. Furthermore, the hyperparameter tuning of the ConvLSTM method is accomplished through SBO algorithm. The experimental validation of the SBODL-FCC technique is validated on UAV image database and the results are inspected under different aspects. The simulation outcomes inferred that the SBODL-FCC technique reaches better performance over other models in terms of several performance measures.