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A CMOS power amplifier (PA) for a UHF (860-960 MHz) stationary RFID reader is presented. To design a high power and power efficient CMOS PA, quasi four pair structure and integrated passive device (IPD) transformers are used. An amplitude modulation is performed through the cascode gate with a pulse shaping filter. The chips are fabricated in a 0.18 m CMOS process and IPD. Measurements show output power of 32.8-33.37 dBm and the power added efficiency (PAE) of 51.8-56.1% with the supply voltage 3.0 V. Index Terms-Class-E, CMOS RF power amplifier, integrated passive device (IPD), quasi four pair, stationary RFID reader.

A fully-integrated Watt-level output O.13llm CMOS power amplifier (PA) based on zero-voltage-switching contour control is presented. The technique employs duty-cycle modulation in concert with outphasing to achieve up to 1.5 times improvement in back-off efficiency compared to conventional outphasing PA. The PA meets EVM and ACLR specifications for WCDMA and LTE 10MHz uplink signals with 29% and 21 % PAE respectively.

A CMOS radio frequency (RF) polar transmitter architecture for a UHF (860-960 MHz) RF identification (RFID) reader is proposed, which consists of a switch-mode CMOS power amplifier (PA) and an analog pulse-shaping filter implemented in 0.25-m CMOS process. The amplitude modulation of a amplitude shift keying signal is performed by simply switching the common gate transistor of a cascode power amplifier. Extremely low power consumption is achieved when the PA is switched off. The power efficiency of the transmitter is enhanced not only by using switching power amplifier but also by employing this architecture.Index Terms-Amplitude shift keying (ASK), CMOS power amplifier, polar transmitter, radio-frequency identification (RFID) reader.

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