No abstract

No abstract

An appropriate solution is suggested for synthesizing wafer-scale, continuous, and stoichiometric MoS2 layers with spatial homogeneity at the low temperature of 450 °C. It is also demonstrated that the MoS2 -based visible-light photodetector arrays are both fabricated on 4 inch SiO2 /Si wafer and polyimide films, revealing 100% active devices with a narrow photocurrent distribution and excellent mechanical durability.

There has been huge interest in advanced nanoelectronic devices based on graphene layers due to their remarkable electrical properties, which include extremely high carrier mobility and the linear energy dispersion relationship. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] However, a lack of methods for mass-production remains a major obstacle for the implementation of these devices in practical applications. The mass fabrication of graphene-based electrical devices requires precise control over the location of the graphene channels on a solid substrate. In addition, for high-performance integrated devices, one should be able to combine graphene devices with high-k dielectrics and control the carrier density in the graphene layers. The conventional doping method that involves the implantation of impurity atoms, however, is not suitable for the integrated devices based on pristine graphene since it will cause permanent damage.[17] Herein, we report a new method for large-scale assembly of graphene oxide (GO) for the fabrication of ambipolar memory devices. In this approach, GO is selectively assembled onto positively charged molecular layers and reduced to obtain the desired device properties. Using this technique, we demonstrate the fabrication and effective operation of floatinggate memory devices. To this end, we sequentially perform the deposition of a dielectric film over the top of a reduced GO junction, the assembly of nanoparticles (NPs), and the fabrication of a top gate. As a proof of concept, we successfully demonstrate that this device can be operated as both conventional conductivityswitching memory and new type-switching memory by adjusting the charge density on the NPs. Importantly, since our method uses only microfabrication processes, it can be utilized immediately by the semiconductor industry and should be a major breakthrough in building innovative electronics.Our memory devices comprise reduced GO pieces and gold NPs that are fabricated by combining the assembly process of nanostructures with conventional microfabrication (Fig.

Nanowires and nanotubes are drawing a tremendous amount of attention due to their potential applications in various nanoscale devices, such as field-effect transistors (FETs), [1±4] chemical and biological sensors, [5±8] nanoprobes, [9] and nanocables.[10] Divanadium pentoxide (V 2 O 5 ) nanowires or nanotubes have been utilized in FETs, [11] sensors, [12,13] spintronic devices, [14] and nanolithography templates. [15,16] However, previous reports have only shown the fabrication of a few devices, so the lack of a mass-production method is holding back their practical applications. Since nanowires are usually synthesized in a solution or powder form, individual nanowires have to be picked up and assembled onto the substrate to build functional devices, which cannot be achieved by conventional microfabrication strategies. Previous techniques used for nanowire assembly include flow-cell methods, [17] electromagnetic-field alignment, [18] biomolecular methods, [19] etc. [20±23] However, since these methods often rely on external forces to precisely align nanowires, it can be a time-consuming task to produce a large number of nanowire circuits with arbitrary orientations. In addition, the surface functionalization of nanowires in some techniques may even change the properties of the nanowires. Herein, we report a simple but efficient method named ªsurface-programmed assemblyº for high-precision assembly and alignment of a large number of pristine V 2 O 5 nanowires on solid substrates. In this strategy, positively charged surface molecular patterns are utilized to assemble and align millions of V 2 O 5 nanowires over a large surface area, while neutral surface molecular patterns are utilized to avoid any unwanted adsorption of nanowires. This method does not rely on any external force for nanowire alignment, and it is compatible with conventional microfabrication processes. Significantly, we demonstrate precision assembly and alignment of V 2 O 5 nanowire arrays and nanowire-based devices over a large surface area (~1 cm 1 cm). This method may pave the way toward industrial-level production of V 2 O 5 nanowire-based devices for practical applications. Figure 1 shows the schematic diagram of our strategy. First, we patterned the substrates with a self-assembled monolayer (SAM) of molecules with positively charged and neutral terminal groups. For example, on Au surfaces, we utilized cysteamine or 2-mercaptoimidazole (2-MI) as a positively charged SAM molecule, while 1-octadecanethiol (ODT) was utilized as a neutral molecular species. On SiO 2 surfaces, aminopropylethoxysilane (APTES) and 1-octadecyltrichlorosilane (OTS) were utilized as positively charged and neutral SAM molecular species, respectively. The molecular patterning process was carried out by patterning the first molecular species via dip-pen nanolithography (DPN), [24±26] Figure 1. Schematic diagram depicting ªsurface-programmed assemblyº of V 2 O 5 nanowires on solid substrates. a) Patterning a self-assembled monolayer with positively charged and neut...