Power consumption is a critical design factor in modern mobile chip design, in which the memory system with dynamic random-access memory (DRAM) consumes more than half of the entire system’s power. Without DRAM bandwidth compression, extreme multimedia operations such as 8K high dynamic range (HDR) recording and 8K video conference calling are not possible without sacrificing image quality or trimming because of thermal limitations or battery time sustainability constraints. Since heterogeneous processors are substantially involved in managing various types of fallbacks or software solutions, complicated compression algorithms for high-compression ratios are not actually adaptable owing to timing closure problems or high throughput requirements. In this paper, we propose evaluation metrics to assess lossless embedded compression (LEC) algorithms to reflect realistic design considerations for mobile multimedia scenarios. Furthermore, we introduce an optimized LEC implementation for contemporary multimedia applications in mobile devices based on the proposed metrics. The proposed LEC implementation enhances the compression ratio of LEC algorithms in other commercial application processors for contemporary premium smartphones by up to 9.2% on average, while maintaining the same timing closure condition.

Abstract. Due to the development of wireless internet and an increasing number of internet users, transferring and receiving errorless data in real-time can be the most important method to guarantee the QoS (Quality of Service) of internet. Convolutional encoding and Viterbi decoding are the widely used techniques to enhance the performance of BER (bit error rate) in the application area such as satellite communications systems. As a method to enhance the QoS of internet, a new DSP architecture that can effectively materialize the Viterbi algorithm, one of the algorithms that can correct errors during data transfer, is introduced in this paper. A new architecture and a new instruction set, which can handle the Viterbi algorithm faster, and simplify the Euclidean distance calculation, are defined. The performance assessment result shows that the proposed DSP can execute the Viterbi algorithm faster than other DSPs. Using 0.18 µm CMOS technology, the new DSP operates in 100 MHz, and consumes 218 µA/MHz.