The evolution of the embedded cores-based design paradigm in recent times has created numerous challenging problems for the test design community. To develop suitable test environment and appropriate test methodologies for digital cores-based system-on-chip (SOC) is a fascinating area of research today. This paper attempts to develop viable solution option to these problems based on cores constructed from the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits. The wrapper that separates the core under test from other cores is assumed to be Institute of Electrical and Electronics Engineers P1500-compliant. The cores and test access mechanism (TAM) are described in the paper using Verilog hardware description language, while TAM is implemented as a plain signal transport medium, being shared by all the cores in the SOC. The fault injection is done by a simulator that also generates the tests for the core. The fault simulation process is carried out after successful compilation of the cores, the individual core selection being done by the program running in the background. He has published numerous papers in the areas of switching and automata theory, digital logic design, threshold logic, fault-tolerant computing, built-in self-test with emphasis on embedded cores-based system-on-chip, microprogramming and microarchitecture, microcode optimization, applied theory of graphs and combinatorics. Dr. Das has served on the technical program committees and organizing committees of many IEEE and non-IEEE international conferences, symposia, and workshops and has acted as Session Organizer,